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@@ -214,6 +214,7 @@
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<Item Name="whitespace.ctl" Type="VI" URL="/<vilib>/Utility/error.llb/whitespace.ctl"/>
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<Item Name="whitespace.ctl" Type="VI" URL="/<vilib>/Utility/error.llb/whitespace.ctl"/>
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</Item>
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</Item>
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<Item Name="lvanlys.dll" Type="Document" URL="/<resource>/lvanlys.dll"/>
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<Item Name="lvanlys.dll" Type="Document" URL="/<resource>/lvanlys.dll"/>
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+ <Item Name="matscript.dll" Type="Document"/>
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<Item Name="mscorlib" Type="VI" URL="mscorlib">
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<Item Name="mscorlib" Type="VI" URL="mscorlib">
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<Property Name="NI.PreserveRelativePath" Type="Bool">true</Property>
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<Property Name="NI.PreserveRelativePath" Type="Bool">true</Property>
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</Item>
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</Item>
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@@ -280,7 +281,7 @@
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</Item>
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</Item>
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<Item Name="NI-sbRIO-9638-02176AD8" Type="RT Single-Board RIO">
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<Item Name="NI-sbRIO-9638-02176AD8" Type="RT Single-Board RIO">
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<Property Name="alias.name" Type="Str">NI-sbRIO-9638-02176AD8</Property>
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<Property Name="alias.name" Type="Str">NI-sbRIO-9638-02176AD8</Property>
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- <Property Name="alias.value" Type="Str">192.168.1.30</Property>
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+ <Property Name="alias.value" Type="Str">192.168.137.30</Property>
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<Property Name="CCSymbols" Type="Str">TARGET_TYPE,RT;OS,Linux;CPU,x64;DeviceCode,7A3B;</Property>
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<Property Name="CCSymbols" Type="Str">TARGET_TYPE,RT;OS,Linux;CPU,x64;DeviceCode,7A3B;</Property>
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<Property Name="crio.ControllerPID" Type="Str">7A3B</Property>
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<Property Name="crio.ControllerPID" Type="Str">7A3B</Property>
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<Property Name="host.ResponsivenessCheckEnabled" Type="Bool">true</Property>
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<Property Name="host.ResponsivenessCheckEnabled" Type="Bool">true</Property>
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@@ -382,6 +383,7 @@ AddOutputFilter chunkFilter
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</CLIPDeclarationSet></Property>
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</CLIPDeclarationSet></Property>
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<Property Name="NI.LV.FPGA.CompileConfigString" Type="Str">sbRIO-9638/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSSBRIO_9638FPGA_TARGET_FAMILYARTIX7TARGET_TYPEFPGA</Property>
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<Property Name="NI.LV.FPGA.CompileConfigString" Type="Str">sbRIO-9638/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSSBRIO_9638FPGA_TARGET_FAMILYARTIX7TARGET_TYPEFPGA</Property>
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<Property Name="NI.LV.FPGA.Version" Type="Int">6</Property>
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<Property Name="NI.LV.FPGA.Version" Type="Int">6</Property>
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+ <Property Name="niFpga_TopLevelVIID" Type="Path">/D/HydraulicControlSystem/FPGA/FPGA_Main.vi</Property>
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<Property Name="Resource Name" Type="Str">RIO0</Property>
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<Property Name="Resource Name" Type="Str">RIO0</Property>
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<Property Name="SWEmulationSubMode" Type="UInt">1</Property>
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<Property Name="SWEmulationSubMode" Type="UInt">1</Property>
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<Property Name="SWEmulationVIPath" Type="Path"></Property>
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<Property Name="SWEmulationVIPath" Type="Path"></Property>
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@@ -2859,7 +2861,6 @@ AddOutputFilter chunkFilter
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<Item Name="FlpLib Add Shared Instance 4.vi" Type="VI" URL="/<userlib>/_NI FLP Library/FPGA/outsideSCTL/FlpLib Add Shared Instance 4.vi"/>
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<Item Name="FlpLib Add Shared Instance 4.vi" Type="VI" URL="/<userlib>/_NI FLP Library/FPGA/outsideSCTL/FlpLib Add Shared Instance 4.vi"/>
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<Item Name="FlpLib Add SCTL Latency 0.vi" Type="VI" URL="/<userlib>/_NI FLP Library/FPGA/insideSCTL/FlpLib Add SCTL Latency 0.vi"/>
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<Item Name="FlpLib Add SCTL Latency 0.vi" Type="VI" URL="/<userlib>/_NI FLP Library/FPGA/insideSCTL/FlpLib Add SCTL Latency 0.vi"/>
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</Item>
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</Item>
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- <Item Name="RT Status.ctl" Type="VI" URL="../RT/Controls/RT Status.ctl"/>
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</Item>
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</Item>
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<Item Name="程序生成规范" Type="Build">
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<Item Name="程序生成规范" Type="Build">
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<Item Name="FPGA_Main" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
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<Item Name="FPGA_Main" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
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@@ -2890,7 +2891,7 @@ AddOutputFilter chunkFilter
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<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
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<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
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<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
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<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
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<Property Name="DestinationDirectory" Type="Path">FPGA/FPGA Bitfiles</Property>
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<Property Name="DestinationDirectory" Type="Path">FPGA/FPGA Bitfiles</Property>
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- <Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/D/SourceCode/LabVIEW/HydraulicControlSystem/FPGA/FPGA Bitfiles/液压台.lvbitx</Property>
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+ <Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/D/HydraulicControlSystem/FPGA/FPGA Bitfiles/液压台.lvbitx</Property>
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<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA/FPGA Bitfiles/液压台.lvbitx</Property>
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<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA/FPGA Bitfiles/液压台.lvbitx</Property>
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<Property Name="ProjectPath" Type="Path">/E/程序/样机/HydraulicControlSystem/液压台控制.lvproj</Property>
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<Property Name="ProjectPath" Type="Path">/E/程序/样机/HydraulicControlSystem/液压台控制.lvproj</Property>
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<Property Name="RelativePath" Type="Bool">true</Property>
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<Property Name="RelativePath" Type="Bool">true</Property>
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