10 ay önce · e39eee884b
--- a/FPGA/FPGA_支撑力积分.vi
+++ b/FPGA/FPGA_支撑力积分.vi
--- a/RT/Config/RT_WriteDropTable.vi
+++ b/RT/Config/RT_WriteDropTable.vi
--- a/RT/Config/RT_WriteRiseTable.vi
+++ b/RT/Config/RT_WriteRiseTable.vi
--- a/RT/Config/RT_WriteSignalGenStart.vi
+++ b/RT/Config/RT_WriteSignalGenStart.vi
--- a/RT/Config/RT_WriteSignalGenStop.vi
+++ b/RT/Config/RT_WriteSignalGenStop.vi
--- a/RT/Config/RT_WriteTroubleshooting.vi
+++ b/RT/Config/RT_WriteTroubleshooting.vi
--- a/RT/Config/RT_WriteValveBlocking.vi
+++ b/RT/Config/RT_WriteValveBlocking.vi
--- a/RT/Config/RT_WriteValvePower.vi
+++ b/RT/Config/RT_WriteValvePower.vi
--- a/RT/Config/RT_WriteZeroChange.vi
+++ b/RT/Config/RT_WriteZeroChange.vi
--- a/RT/RT_Config.vi
+++ b/RT/RT_Config.vi
--- a/RT/RT_DisplacementFinetuning.vi
+++ b/RT/RT_DisplacementFinetuning.vi
--- a/RT/RT_Init.vi
+++ b/RT/RT_Init.vi
--- a/RT/RT_ReadConfig.vi
+++ b/RT/RT_ReadConfig.vi
--- a/RT/RT_WaitTrigger.vi
+++ b/RT/RT_WaitTrigger.vi
--- a/RT/RT_WriteConfig.vi
+++ b/RT/RT_WriteConfig.vi
--- a/液压台控制.lvproj
+++ b/液压台控制.lvproj
@@ -2147,6 +2147,7 @@ AddOutputFilter chunkFilter
 
				 						<Item Name="niFPGA BW CU Order 2 (32-bit).vi" Type="VI" URL="/&lt;vilib&gt;/rvi/Analysis/measure/butterworth/templates/niFPGA BW CU Order 2 (32-bit).vi"/>
			
 
				 						<Item Name="lvSimController.dll" Type="Document" URL="/&lt;vilib&gt;/rvi/Simulation/lvSimController.dll"/>
			
 
				 					</Item>
			
 
				+					<Item Name="RT Status.ctl" Type="VI" URL="../RT/Controls/RT Status.ctl"/>
			
 
				 				</Item>
			
 
				 				<Item Name="程序生成规范" Type="Build">
			
 
				 					<Item Name="FPGA_Main" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
			
--- a/液压台控制.vi
+++ b/液压台控制.vi
--- a/液压台控制/SubVIs/液压台控制_参数设置.vi
+++ b/液压台控制/SubVIs/液压台控制_参数设置.vi
--- a/液压台控制/SubVIs/液压台控制_系统调试.vi
+++ b/液压台控制/SubVIs/液压台控制_系统调试.vi