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@@ -168,88 +168,330 @@ namespace NIFPGA
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switch (reg.Datatype)
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switch (reg.Datatype)
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{
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{
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case lvbitx.Datatype.Int16:
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case lvbitx.Datatype.Int16:
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- properties.Add(new FPGAProperty<short>(session, reg.Offset, reg.Indicator)
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+ if(!reg.Indicator)
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{
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{
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- Name= reg.Name,
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- });
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+
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+ properties.Add(new FPGAWriteProperty<short>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<short>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Boolean:
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case lvbitx.Datatype.Boolean:
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- properties.Add(new FPGAProperty<bool>(session, reg.Offset, reg.Indicator)
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<bool>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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{
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{
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- Name = reg.Name,
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- });
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+ properties.Add(new FPGAReadProperty<bool>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int8:
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case lvbitx.Datatype.Int8:
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- properties.Add(new FPGAProperty<sbyte>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<sbyte>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<sbyte>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint8:
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case lvbitx.Datatype.Uint8:
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- properties.Add(new FPGAProperty<byte>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<byte>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<byte>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint16:
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case lvbitx.Datatype.Uint16:
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- properties.Add(new FPGAProperty<ushort>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<ushort>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<ushort>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int32:
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case lvbitx.Datatype.Int32:
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- properties.Add(new FPGAProperty<int>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<int>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<int>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint32:
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case lvbitx.Datatype.Uint32:
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- properties.Add(new FPGAProperty<uint>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<uint>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<uint>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int64:
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case lvbitx.Datatype.Int64:
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- properties.Add(new FPGAProperty<long>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<long>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<long>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint64:
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case lvbitx.Datatype.Uint64:
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- properties.Add(new FPGAProperty<ulong>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<ulong>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<ulong>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Float:
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case lvbitx.Datatype.Float:
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- properties.Add(new FPGAProperty<float>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<float>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<float>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Double:
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case lvbitx.Datatype.Double:
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- properties.Add(new FPGAProperty<double>(session, reg.Offset, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+
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+ properties.Add(new FPGAWriteProperty<double>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAReadProperty<double>(session, reg.Offset)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.FXP:
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case lvbitx.Datatype.FXP:
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- properties.Add(new FPGAFXPProperty(session, reg.Offset, reg.FxpTypeInfo,_FXPConvert, reg.Indicator)
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAFXPWriteProperty(session, reg.Offset, reg.FxpTypeInfo, _FXPConvert)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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+ else
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{
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{
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- Name = reg.Name,
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- });
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+ properties.Add(new FPGAFXPReadProperty(session, reg.Offset, reg.FxpTypeInfo, _FXPConvert)
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+ {
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+ Name = reg.Name,
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+ });
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+ }
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break;
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break;
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case lvbitx.Datatype.Array:
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case lvbitx.Datatype.Array:
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switch (reg.ArrayValueType)
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switch (reg.ArrayValueType)
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{
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{
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case lvbitx.Datatype.Boolean:
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case lvbitx.Datatype.Boolean:
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- properties.Add(new FPGAArrayProperty<bool>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if(!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<bool>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<bool>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int8:
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case lvbitx.Datatype.Int8:
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- properties.Add(new FPGAArrayProperty<sbyte>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<sbyte>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<sbyte>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint8:
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case lvbitx.Datatype.Uint8:
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- properties.Add(new FPGAArrayProperty<byte>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<byte>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<byte>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int16:
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case lvbitx.Datatype.Int16:
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- properties.Add(new FPGAArrayProperty<short>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<short>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<short>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint16:
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case lvbitx.Datatype.Uint16:
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- properties.Add(new FPGAArrayProperty<short>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<ushort>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<ushort>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int32:
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case lvbitx.Datatype.Int32:
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- properties.Add(new FPGAArrayProperty<int>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<int>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<int>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint32:
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case lvbitx.Datatype.Uint32:
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- properties.Add(new FPGAArrayProperty<uint>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<uint>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<uint>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Int64:
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case lvbitx.Datatype.Int64:
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- properties.Add(new FPGAArrayProperty<long>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<long>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<long>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Uint64:
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case lvbitx.Datatype.Uint64:
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- properties.Add(new FPGAArrayProperty<ulong>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<ulong>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<ulong>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Float:
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case lvbitx.Datatype.Float:
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- properties.Add(new FPGAArrayProperty<float>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
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+ {
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+ properties.Add(new FPGAArrayWriteProperty<float>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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+ else
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+ {
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+ properties.Add(new FPGAArrayReadProperty<float>(session, reg.Offset, reg.Size) { Name = reg.Name });
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+ }
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break;
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break;
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case lvbitx.Datatype.Double:
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case lvbitx.Datatype.Double:
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- properties.Add(new FPGAArrayProperty<double>(session, reg.Offset, reg.Size, reg.Indicator) { Name = reg.Name });
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+ if (!reg.Indicator)
|
|
|
|
+ {
|
|
|
|
+ properties.Add(new FPGAArrayWriteProperty<double>(session, reg.Offset, reg.Size) { Name = reg.Name });
|
|
|
|
+ }
|
|
|
|
+ else
|
|
|
|
+ {
|
|
|
|
+ properties.Add(new FPGAArrayReadProperty<double>(session, reg.Offset, reg.Size) { Name = reg.Name });
|
|
|
|
+ }
|
|
break;
|
|
break;
|
|
case lvbitx.Datatype.FXP:
|
|
case lvbitx.Datatype.FXP:
|
|
- properties.Add(new FPGAArrayFXPProperty(session, reg.Offset, reg.Size, reg.FxpTypeInfo,_FXPConvert) { Name = reg.Name });
|
|
|
|
|
|
+ if (!reg.Indicator)
|
|
|
|
+ {
|
|
|
|
+ properties.Add(new FPGAArrayFXPWriteProperty(session, reg.Offset, reg.Size, reg.FxpTypeInfo, _FXPConvert) { Name = reg.Name });
|
|
|
|
+ }
|
|
|
|
+ else
|
|
|
|
+ {
|
|
|
|
+ properties.Add(new FPGAArrayFXPReadProperty(session, reg.Offset, reg.Size, reg.FxpTypeInfo, _FXPConvert) { Name = reg.Name });
|
|
|
|
+ }
|
|
break;
|
|
break;
|
|
case lvbitx.Datatype.Array:
|
|
case lvbitx.Datatype.Array:
|
|
break;
|
|
break;
|