namespace NIFPGA { public enum NiFpga_Status { Success = 0, /** * The timeout expired before the FIFO operation could complete. */ FifoTimeout = -50400, /** * No transfer is in progress because the transfer was aborted by the client. * The operation could not be completed as specified. */ TransferAborted = -50405, /** * A memory allocation failed. Try again after rebooting. */ MemoryFull = -52000, /** * An unexpected software error occurred. */ SoftwareFault = -52003, /** * A parameter to a function was not valid. This could be a NULL pointer, a bad * value, etc. */ InvalidParameter = -52005, /** * A required resource was not found. The NiFpga.* library, the RIO resource, or * some other resource may be missing. */ ResourceNotFound = -52006, /** * A required resource was not properly initialized. This could occur if * NiFpga_Initialize was not called or a required NiFpga_IrqContext was not * reserved. */ ResourceNotInitialized = -52010, /** * The FPGA is already running. */ FpgaAlreadyRunning = -61003, /** * An error occurred downloading the VI to the FPGA device. Verify that * the target is connected and powered and that the resource of the target * is properly configured. */ DownloadError = -61018, /** * The bitfile was not compiled for the specified resource's device type. */ DeviceTypeMismatch = -61024, /** * An error was detected in the communication between the host computer and the * FPGA target. */ CommunicationTimeout = -61046, /** * The timeout expired before any of the IRQs were asserted. */ IrqTimeout = -61060, /** * The specified bitfile is invalid or corrupt. */ CorruptBitfile = -61070, /** * The requested FIFO depth is invalid. It is either 0 or an amount not * supported by the hardware. */ BadDepth = -61072, /** * The number of FIFO elements is invalid. Either the number is greater than the * depth of the host memory DMA FIFO, or more elements were requested for * release than had been acquired. */ BadReadWriteCount = -61073, /** * A hardware clocking error occurred. A derived clock lost lock with its base * clock during the execution of the LabVIEW FPGA VI. If any base clocks with * derived clocks are referencing an external source, make sure that the * external source is connected and within the supported frequency, jitter, * accuracy, duty cycle, and voltage specifications. Also verify that the * characteristics of the base clock match the configuration specified in the * FPGA Base Clock Properties. If all base clocks with derived clocks are * generated from free-running, on-board sources, please contact National * Instruments technical support at ni.com/support. */ ClockLostLock = -61083, /** * The operation could not be performed because the FPGA is busy. Stop all * activities on the FPGA before requesting this operation. If the target is in * Scan Interface programming mode, put it in FPGA Interface programming mode. */ FpgaBusy = -61141, /** * The operation could not be performed because the FPGA is busy operating in * FPGA Interface C API mode. Stop all activities on the FPGA before requesting * this operation. */ FpgaBusyFpgaInterfaceCApi = -61200, /** * The chassis is in Scan Interface programming mode. In order to run FPGA VIs, * you must go to the chassis properties page, select FPGA programming mode, and * deploy settings. */ FpgaBusyScanInterface = -61201, /** * The operation could not be performed because the FPGA is busy operating in * FPGA Interface mode. Stop all activities on the FPGA before requesting this * operation. */ FpgaBusyFpgaInterface = -61202, /** * The operation could not be performed because the FPGA is busy operating in * Interactive mode. Stop all activities on the FPGA before requesting this * operation. */ FpgaBusyInteractive = -61203, /** * The operation could not be performed because the FPGA is busy operating in * Emulation mode. Stop all activities on the FPGA before requesting this * operation. */ FpgaBusyEmulation = -61204, /** * LabVIEW FPGA does not support the Reset method for bitfiles that allow * removal of implicit enable signals in single-cycle Timed Loops. */ ResetCalledWithImplicitEnableRemoval = -61211, /** * LabVIEW FPGA does not support the Abort method for bitfiles that allow * removal of implicit enable signals in single-cycle Timed Loops. */ AbortCalledWithImplicitEnableRemoval = -61212, /** * LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles * that allow removal of implicit enable signals in single-cycle Timed Loops. * Pass the NiFpga_CloseAttribute_NoResetIfLastSession attribute to NiFpga_Close * instead of 0. */ CloseAndResetCalledWithImplicitEnableRemoval = -61213, /** * For bitfiles that allow removal of implicit enable signals in single-cycle * Timed Loops, LabVIEW FPGA does not support this method prior to running the * bitfile. */ ImplicitEnableRemovalButNotYetRun = -61214, /** * Bitfiles that allow removal of implicit enable signals in single-cycle Timed * Loops can run only once. Download the bitfile again before re-running the VI. */ RunAfterStoppedCalledWithImplicitEnableRemoval = -61215, /** * A gated clock has violated the handshaking protocol. If you are using * external gated clocks, ensure that they follow the required clock gating * protocol. If you are generating your clocks internally, please contact * National Instruments Technical Support. */ GatedClockHandshakingViolation = -61216, /** * The number of elements requested must be less than or equal to the number of * unacquired elements left in the host memory DMA FIFO. There are currently * fewer unacquired elements left in the FIFO than are being requested. Release * some acquired elements before acquiring more elements. */ ElementsNotPermissibleToBeAcquired = -61219, /** * The operation could not be performed because the FPGA is in configuration or * discovery mode. Wait for configuration or discovery to complete and retry * your operation. */ FpgaBusyConfiguration = -61252, /** * LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles * that do not support Reset. Pass the * NiFpga_CloseAttribute_NoResetIfLastSession attribute to NiFpga_Close instead * of 0. */ CloseAndResetCalledWithResetNotSupported = -61253, /** * An unexpected internal error occurred. */ InternalError = -61499, /** * The NI-RIO driver was unable to allocate memory for a FIFO. This can happen * when the combined depth of all DMA FIFOs exceeds the maximum depth for the * controller, or when the controller runs out of system memory. You may be able * to reconfigure the controller with a greater maximum FIFO depth. For more * information, refer to the NI KnowledgeBase article 65OF2ERQ. */ TotalDmaFifoDepthExceeded = -63003, /** * Access to the remote system was denied. Use MAX to check the Remote Device * Access settings under Software>>NI-RIO>>NI-RIO Settings on the remote system. */ AccessDenied = -63033, /** * The NI-RIO software on the host is not compatible with the software on the * target. Upgrade the NI-RIO software on the host in order to connect to this * target. */ HostVersionMismatch = -63038, /** * A connection could not be established to the specified remote device. Ensure * that the device is on and accessible over the network, that NI-RIO software * is installed, and that the RIO server is running and properly configured. */ RpcConnectionError = -63040, /** * The RPC session is invalid. The target may have reset or been rebooted. Check * the network connection and retry the operation. */ RpcSessionError = -63043, /** * The operation could not complete because another session is accessing the * FIFO. Close the other session and retry. */ FifoReserved = -63082, /** * A Configure FIFO, Stop FIFO, Read FIFO, or Write FIFO function was called * while the host had acquired elements of the FIFO. Release all acquired * elements before configuring, stopping, reading, or writing. */ FifoElementsCurrentlyAcquired = -63083, /** * A function was called using a misaligned address. The address must be a * multiple of the size of the datatype. */ MisalignedAccess = -63084, /** * The FPGA Read/Write Control Function is accessing a control or indicator * with data that exceeds the maximum size supported on the current target. * Refer to the hardware documentation for the limitations on data types for * this target. */ ControlOrIndicatorTooLarge = -63085, /** * A valid .lvbitx bitfile is required. If you are using a valid .lvbitx * bitfile, the bitfile may not be compatible with the software you are using. * Determine which version of LabVIEW was used to make the bitfile, update your * software to that version or later, and try again. */ BitfileReadError = -63101, /** * The specified signature does not match the signature of the bitfile. If the * bitfile has been recompiled, regenerate the C API and rebuild the * application. */ SignatureMismatch = -63106, /** * The bitfile you are trying to use is incompatible with the version * of NI-RIO installed on the target and/or host. Update the version * of NI-RIO on the target and/or host to the same version (or later) * used to compile the bitfile. Alternatively, recompile the bitfile * with the same version of NI-RIO that is currently installed on the * target and/or host. */ IncompatibleBitfile = -63107, /** * A hardware failure has occurred. The operation could not be completed as * specified. */ HardwareFault = -63150, /** * Either the supplied resource name is invalid as a RIO resource name, or the * device was not found. Use MAX to find the proper resource name for the * intended device. */ InvalidResourceName = -63192, /** * The requested feature is not supported. */ FeatureNotSupported = -63193, /** * The NI-RIO software on the target system is not compatible with this * software. Upgrade the NI-RIO software on the target system. */ VersionMismatch = -63194, /** * The session is invalid or has been closed. */ InvalidSession = -63195, /** * The maximum number of open FPGA sessions has been reached. Close some open * sessions. */ OutOfHandles = -63198, } }