NiFpga_Status.cs 11 KB

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  1. 
  2. namespace NIFPGA
  3. {
  4. public enum NiFpga_Status
  5. {
  6. Success = 0,
  7. /**
  8. * The timeout expired before the FIFO operation could complete.
  9. */
  10. FifoTimeout = -50400,
  11. /**
  12. * No transfer is in progress because the transfer was aborted by the client.
  13. * The operation could not be completed as specified.
  14. */
  15. TransferAborted = -50405,
  16. /**
  17. * A memory allocation failed. Try again after rebooting.
  18. */
  19. MemoryFull = -52000,
  20. /**
  21. * An unexpected software error occurred.
  22. */
  23. SoftwareFault = -52003,
  24. /**
  25. * A parameter to a function was not valid. This could be a NULL pointer, a bad
  26. * value, etc.
  27. */
  28. InvalidParameter = -52005,
  29. /**
  30. * A required resource was not found. The NiFpga.* library, the RIO resource, or
  31. * some other resource may be missing.
  32. */
  33. ResourceNotFound = -52006,
  34. /**
  35. * A required resource was not properly initialized. This could occur if
  36. * NiFpga_Initialize was not called or a required NiFpga_IrqContext was not
  37. * reserved.
  38. */
  39. ResourceNotInitialized = -52010,
  40. /**
  41. * The FPGA is already running.
  42. */
  43. FpgaAlreadyRunning = -61003,
  44. /**
  45. * An error occurred downloading the VI to the FPGA device. Verify that
  46. * the target is connected and powered and that the resource of the target
  47. * is properly configured.
  48. */
  49. DownloadError = -61018,
  50. /**
  51. * The bitfile was not compiled for the specified resource's device type.
  52. */
  53. DeviceTypeMismatch = -61024,
  54. /**
  55. * An error was detected in the communication between the host computer and the
  56. * FPGA target.
  57. */
  58. CommunicationTimeout = -61046,
  59. /**
  60. * The timeout expired before any of the IRQs were asserted.
  61. */
  62. IrqTimeout = -61060,
  63. /**
  64. * The specified bitfile is invalid or corrupt.
  65. */
  66. CorruptBitfile = -61070,
  67. /**
  68. * The requested FIFO depth is invalid. It is either 0 or an amount not
  69. * supported by the hardware.
  70. */
  71. BadDepth = -61072,
  72. /**
  73. * The number of FIFO elements is invalid. Either the number is greater than the
  74. * depth of the host memory DMA FIFO, or more elements were requested for
  75. * release than had been acquired.
  76. */
  77. BadReadWriteCount = -61073,
  78. /**
  79. * A hardware clocking error occurred. A derived clock lost lock with its base
  80. * clock during the execution of the LabVIEW FPGA VI. If any base clocks with
  81. * derived clocks are referencing an external source, make sure that the
  82. * external source is connected and within the supported frequency, jitter,
  83. * accuracy, duty cycle, and voltage specifications. Also verify that the
  84. * characteristics of the base clock match the configuration specified in the
  85. * FPGA Base Clock Properties. If all base clocks with derived clocks are
  86. * generated from free-running, on-board sources, please contact National
  87. * Instruments technical support at ni.com/support.
  88. */
  89. ClockLostLock = -61083,
  90. /**
  91. * The operation could not be performed because the FPGA is busy. Stop all
  92. * activities on the FPGA before requesting this operation. If the target is in
  93. * Scan Interface programming mode, put it in FPGA Interface programming mode.
  94. */
  95. FpgaBusy = -61141,
  96. /**
  97. * The operation could not be performed because the FPGA is busy operating in
  98. * FPGA Interface C API mode. Stop all activities on the FPGA before requesting
  99. * this operation.
  100. */
  101. FpgaBusyFpgaInterfaceCApi = -61200,
  102. /**
  103. * The chassis is in Scan Interface programming mode. In order to run FPGA VIs,
  104. * you must go to the chassis properties page, select FPGA programming mode, and
  105. * deploy settings.
  106. */
  107. FpgaBusyScanInterface = -61201,
  108. /**
  109. * The operation could not be performed because the FPGA is busy operating in
  110. * FPGA Interface mode. Stop all activities on the FPGA before requesting this
  111. * operation.
  112. */
  113. FpgaBusyFpgaInterface = -61202,
  114. /**
  115. * The operation could not be performed because the FPGA is busy operating in
  116. * Interactive mode. Stop all activities on the FPGA before requesting this
  117. * operation.
  118. */
  119. FpgaBusyInteractive = -61203,
  120. /**
  121. * The operation could not be performed because the FPGA is busy operating in
  122. * Emulation mode. Stop all activities on the FPGA before requesting this
  123. * operation.
  124. */
  125. FpgaBusyEmulation = -61204,
  126. /**
  127. * LabVIEW FPGA does not support the Reset method for bitfiles that allow
  128. * removal of implicit enable signals in single-cycle Timed Loops.
  129. */
  130. ResetCalledWithImplicitEnableRemoval = -61211,
  131. /**
  132. * LabVIEW FPGA does not support the Abort method for bitfiles that allow
  133. * removal of implicit enable signals in single-cycle Timed Loops.
  134. */
  135. AbortCalledWithImplicitEnableRemoval = -61212,
  136. /**
  137. * LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles
  138. * that allow removal of implicit enable signals in single-cycle Timed Loops.
  139. * Pass the NiFpga_CloseAttribute_NoResetIfLastSession attribute to NiFpga_Close
  140. * instead of 0.
  141. */
  142. CloseAndResetCalledWithImplicitEnableRemoval = -61213,
  143. /**
  144. * For bitfiles that allow removal of implicit enable signals in single-cycle
  145. * Timed Loops, LabVIEW FPGA does not support this method prior to running the
  146. * bitfile.
  147. */
  148. ImplicitEnableRemovalButNotYetRun = -61214,
  149. /**
  150. * Bitfiles that allow removal of implicit enable signals in single-cycle Timed
  151. * Loops can run only once. Download the bitfile again before re-running the VI.
  152. */
  153. RunAfterStoppedCalledWithImplicitEnableRemoval = -61215,
  154. /**
  155. * A gated clock has violated the handshaking protocol. If you are using
  156. * external gated clocks, ensure that they follow the required clock gating
  157. * protocol. If you are generating your clocks internally, please contact
  158. * National Instruments Technical Support.
  159. */
  160. GatedClockHandshakingViolation = -61216,
  161. /**
  162. * The number of elements requested must be less than or equal to the number of
  163. * unacquired elements left in the host memory DMA FIFO. There are currently
  164. * fewer unacquired elements left in the FIFO than are being requested. Release
  165. * some acquired elements before acquiring more elements.
  166. */
  167. ElementsNotPermissibleToBeAcquired = -61219,
  168. /**
  169. * The operation could not be performed because the FPGA is in configuration or
  170. * discovery mode. Wait for configuration or discovery to complete and retry
  171. * your operation.
  172. */
  173. FpgaBusyConfiguration = -61252,
  174. /**
  175. * LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles
  176. * that do not support Reset. Pass the
  177. * NiFpga_CloseAttribute_NoResetIfLastSession attribute to NiFpga_Close instead
  178. * of 0.
  179. */
  180. CloseAndResetCalledWithResetNotSupported = -61253,
  181. /**
  182. * An unexpected internal error occurred.
  183. */
  184. InternalError = -61499,
  185. /**
  186. * The NI-RIO driver was unable to allocate memory for a FIFO. This can happen
  187. * when the combined depth of all DMA FIFOs exceeds the maximum depth for the
  188. * controller, or when the controller runs out of system memory. You may be able
  189. * to reconfigure the controller with a greater maximum FIFO depth. For more
  190. * information, refer to the NI KnowledgeBase article 65OF2ERQ.
  191. */
  192. TotalDmaFifoDepthExceeded = -63003,
  193. /**
  194. * Access to the remote system was denied. Use MAX to check the Remote Device
  195. * Access settings under Software>>NI-RIO>>NI-RIO Settings on the remote system.
  196. */
  197. AccessDenied = -63033,
  198. /**
  199. * The NI-RIO software on the host is not compatible with the software on the
  200. * target. Upgrade the NI-RIO software on the host in order to connect to this
  201. * target.
  202. */
  203. HostVersionMismatch = -63038,
  204. /**
  205. * A connection could not be established to the specified remote device. Ensure
  206. * that the device is on and accessible over the network, that NI-RIO software
  207. * is installed, and that the RIO server is running and properly configured.
  208. */
  209. RpcConnectionError = -63040,
  210. /**
  211. * The RPC session is invalid. The target may have reset or been rebooted. Check
  212. * the network connection and retry the operation.
  213. */
  214. RpcSessionError = -63043,
  215. /**
  216. * The operation could not complete because another session is accessing the
  217. * FIFO. Close the other session and retry.
  218. */
  219. FifoReserved = -63082,
  220. /**
  221. * A Configure FIFO, Stop FIFO, Read FIFO, or Write FIFO function was called
  222. * while the host had acquired elements of the FIFO. Release all acquired
  223. * elements before configuring, stopping, reading, or writing.
  224. */
  225. FifoElementsCurrentlyAcquired = -63083,
  226. /**
  227. * A function was called using a misaligned address. The address must be a
  228. * multiple of the size of the datatype.
  229. */
  230. MisalignedAccess = -63084,
  231. /**
  232. * The FPGA Read/Write Control Function is accessing a control or indicator
  233. * with data that exceeds the maximum size supported on the current target.
  234. * Refer to the hardware documentation for the limitations on data types for
  235. * this target.
  236. */
  237. ControlOrIndicatorTooLarge = -63085,
  238. /**
  239. * A valid .lvbitx bitfile is required. If you are using a valid .lvbitx
  240. * bitfile, the bitfile may not be compatible with the software you are using.
  241. * Determine which version of LabVIEW was used to make the bitfile, update your
  242. * software to that version or later, and try again.
  243. */
  244. BitfileReadError = -63101,
  245. /**
  246. * The specified signature does not match the signature of the bitfile. If the
  247. * bitfile has been recompiled, regenerate the C API and rebuild the
  248. * application.
  249. */
  250. SignatureMismatch = -63106,
  251. /**
  252. * The bitfile you are trying to use is incompatible with the version
  253. * of NI-RIO installed on the target and/or host. Update the version
  254. * of NI-RIO on the target and/or host to the same version (or later)
  255. * used to compile the bitfile. Alternatively, recompile the bitfile
  256. * with the same version of NI-RIO that is currently installed on the
  257. * target and/or host.
  258. */
  259. IncompatibleBitfile = -63107,
  260. /**
  261. * A hardware failure has occurred. The operation could not be completed as
  262. * specified.
  263. */
  264. HardwareFault = -63150,
  265. /**
  266. * Either the supplied resource name is invalid as a RIO resource name, or the
  267. * device was not found. Use MAX to find the proper resource name for the
  268. * intended device.
  269. */
  270. InvalidResourceName = -63192,
  271. /**
  272. * The requested feature is not supported.
  273. */
  274. FeatureNotSupported = -63193,
  275. /**
  276. * The NI-RIO software on the target system is not compatible with this
  277. * software. Upgrade the NI-RIO software on the target system.
  278. */
  279. VersionMismatch = -63194,
  280. /**
  281. * The session is invalid or has been closed.
  282. */
  283. InvalidSession = -63195,
  284. /**
  285. * The maximum number of open FPGA sessions has been reached. Close some open
  286. * sessions.
  287. */
  288. OutOfHandles = -63198,
  289. }
  290. }